Integrated circuit analysis imaging techniques are frequently used during failure analysis of semiconductor devices. Methods for performing this analysis include collection and analysis of emitted radiation, electron microscopy, and conventional optical imaging. The image derived from the analysis method chosen can be examined to determine several characteristics of the invention, which makes the processes especially useful for reverse engineering, failure analysis, and operational analysis. Typically, when the object of the imaging technique is reverse engineering the front side of the integrated circuit is processed and imaged.
Front side imaging allows enhanced viewing of the interconnects, which generally reside on the substrate at the lowest level of the chip. Because the interconnects are a frequent source of failure in an integrated circuit, the ability to clearly view the interconnects greatly reduces the number of defective parts distributed by a manufacturer. It also allows simpler and more accurate failure analysis during the testing phases of product development. Additionally, backside processing provides a clearer view of the components of the integrated circuit as the interconnects do not obscure the view of the electronic components as severely as the components obscure the view of the interconnects in frontside imaging. This again results in more accurate failure and operational analysis.
U.S. Pat. No. 4,680,635, entitled “EMISSION MICROSCOPE,” discloses a device for providing high sensitivity viewing of semiconductors. With the device, a first illuminated top view is taken of a selected portion of the semiconductor. After the image is taken, the illumination is removed and background noise light is collected to create a background image. A voltage is then applied to the device causing leakage current to be conducted through any defects of the semiconductor. This leakage will emit weak visible light and infrared light, which is amplified and captured a second illuminated image. The background image is subtracted from the second illuminated image to produce an improved image, which is superimposed over the first image. This superimposed image is used for failure or operational analysis of the semiconductor. The analysis techniques employed in this patent differ from the method of the present application. U.S. Pat. No. 4,680,635 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 6,107,107, entitled “ANALYZING AN ELECTRONIC CIRCUIT FORMED UPON A FRONTSIDE SURFACE OF A SEMICONDUCTOR SUBSTRATE BY DETECTING RADITATION EXITING A BACKSIDE SURFACE COATED WIH AN ANTIREFLECTIVE MATERIAL,” discloses an imaging system that detects electromagnetic radiation emanating from the backside surface of an integrated circuit. The backside surface is coated with an antireflective coating, a beam of electromagnetic radiation is directed to the backside surface or electrical power is supplied to the circuit, and the radiation emanated from the backside is collected. The emitted radiation is used to analyze the circuit. This method of analysis is not used in the present invention. U.S. Pat. No. 6,107,107 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 6,338,974, entitled “INTEGRATED CIRCUIT ANALYTICAL IMAGING TECHNIQUE EMPLOYING A BACKSIDE SURFACE FILL LAYER,” discloses a method of processing a backside of an integrated circuit to allow analysis of the circuit. With this method, the backside of the circuit is thinned, resulting in a thin semiconductor substrate having peaks and valleys. A fill material is applied to the thin substrate to at least partially fill the valleys. The result is a smother substrate surface. This surface is imaged using any conventional radiation emission imaging technique. The present invention does not use this method for backside imaging. U.S. Pat. No. 6,338,974 is hereby incorporated by reference into the specification of the present invention.
U.S. Pat. No. 6,650,130, entitled “INTEGRATED CIRCUIT DEVICE DEFECT DETECTION METHOD AND APPARATUS EMPLOYING LIGHT EMISSION IMAGING,” discloses a method of detecting defects in integrated circuits by providing electrical power to the circuits and recording the images generated by the light emitted from the circuits due to the application of power. Prior to providing power to the integrated circuits, the backside of the circuits may be thinned and polished if necessary to allow the electrical signals to be transmitted to the integrated circuit. The present invention does not operate in this manner. U.S. Pat. No. 6,650,130 is hereby incorporated by reference into the specification of the present invention.
The difficulty in performing failure analysis or reverse engineering on an integrated circuit is obtaining a clear view of the components of the circuit. To achieve this, most modern systems attempt to obtain a clear image of the top side of the integrated circuit through light emission or a combination of optically obtained images and emitted images. These procedures are extremely costly. Additionally, emitted images often result in a shadowing effect caused by the activation of the interconnect structures and active structures during the application of power or heating of the semiconductor during the imaging process. Surface and subsurface charging cause shadowing. This shadow effect causes blurring around the images under test, and may ultimately obscure portions of the final image. This can cause inaccuracies in the final reading. In the case of reverse engineering this is extremely problematic as the shadows make it difficult to see the overall construction of the device. Moreover, conventional analysis techniques are generally limited to only one imaging method for the integrated circuit. It is therefore desirable in the art to have a simple, cost-effective top side imaging process that allows a clear image to be obtained of the components of an integrated circuit by a variety of imaging methods.